This high speed multi-channel data capture reference design enables optimum system performance. System designers needs to consider critical design parameters like clock jitter and skew for high speed multi-channel clock generation: which affects overall system SNR: SFDR: channel to channel skew and deterministic latency. This reference design demonstrates multi-channel AFE and clock solution using high speed data converters with JESD204B: high speed amplifiers: high performance clocks and low noise power solutions to achieve optimum system performance