This reference design provides the solution for synchronization design challenges associated with emerging 5G adapted applications like massive multiple input multiple output (mMIMO): phase array RADAR and communication payload. The typical RF front end contains antenna: low noise amplifier (LNA): mixer : local oscillator (LO) in analog domain and analog to digital converter: numerical controlled oscillator (NCO) and digital down converter (DDC) in digital domain. To achieve overall system synchronization these digital blocks need to be synchronize with system clock. This reference design uses ADC12DJ3200 data converter: achieve less than 5-ps channel-to-channel skew across multiple receiver with deterministic latency by synchronizing on chip NCO with SYNC~ and uses noiseless aperture delay adjustment (tAD Adjust) feature to further reduce skew. This design also provides a very low phase noise clocking solution based the LMX2594 wide band PLL and the LMK04828 synthesizer and jitter cleaner.