TIDA-00432 Reference Design

Texas Instruments

Synchronization of JESD204B Giga-Sample ADCs using Xilinx Platform for Phased Array Radar Systems


This system level design shows how two ADC12J4000 evaluation modules (EVMs) can be synchronized together using a Xilinx VC707 platform. The design document describes the required hardware modifications and device configurations: including the clocking scheme. Example configuration files are shown for each EVM. The FPGA firmware is described and the relevant Xilinx IP block configuration parameters are shown. Data taken on the actual hardware is shown and analyzed: showing synchronization within 50 ps without characterized cables or calibrated propagation delays.

  • Demonstrates a typical phased array radar sub-system by showing synchronization of JESD204B giga-sample ADCsThe LMK04828 clocking solution used is described in detailTest results show synchronization within 50 ps without any characterization of cables or calibration of propagation delaysXilinx firmware development is discussed to offer a clear understanding of the requirementsThis sub-system is tested and includes example configuration files
  • Oscilloscope (DSO)
  • Vector signal transceiver (VST)
  • Wireless communications test
Product Categories
  • Data converters


Part Number Name Companion Part
ADC12J1600 ADC12J1600 Buy Datasheet
ADC12J2700 ADC12J2700 Buy Datasheet
ADC12J4000 ADC12J4000 Buy Datasheet
LM26400Y LM26400Y Buy Datasheet
LMK04828 LMK04828 Buy Datasheet
LP38513-ADJ LP38513-ADJ Buy Datasheet
LP3878-ADJ LP3878-ADJ Buy Datasheet
TPS54327 TPS54327 Buy Datasheet
TPS74901 TPS74901 Buy Datasheet


Bill Of Materials

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Test Data

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Other Documents

Title Updated Type Size (KB)
TIDA-00432 Gerber 17 Mar 2015 ZIP 712
TIDA-00432 BOM 17 Mar 2015 PDF 140
TIDA-00432 Schematic 17 Mar 2015 PDF 555