Xilinx® Zynq®7000 series (XC7Z015) Power Solution: 5W - Reference Design
Description
The PMP10600.1 reference design provides all the power supply rails necessary to power Xilinx® Zynq® 7000 series (XC7Z015) FPGA. This design uses several LMZ3 series modules: LDOs: and a DDR termination regulator. It also features one LM3880 for power up and power down sequencing. This design uses a 12V input.
Features
- Provides all the power supply rails needed for a Xilinx® Zynq® 7000 series (XC7Z015) Design optimized to support a 12V input On board power up and power down sequencing Supports DDR3 memory device Module design for ease of use
Applications
- Baseband unit (BBU)
- Edge router
- Intra-DC interconnect (metro)
- Inter-DC interconnect (long-haul
- submarine)
- Core router
- Performance client
- High performance computing
- Active antenna system mMIMO (AAS)
- Processor module
- Indoor backhaul
- Campus & branch switches
- Cell site gateway router
- Multi-access edge computing (MEC)
- CT & PET scanner
- Data center switch
- Macro remote radio unit (RRU)
- X-ray systems
Product Categories
- Power management
| Download the bill of materials for PMP10600 | Download |
Design File
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Download the design file for PMP10600Test Data
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Download the test file for PMP10600| Title | Updated | Type | Size (KB) | |
|---|---|---|---|---|
| PMP10600 Gerber | 14 Jan 2015 | ZIP | 9189 | |
| PMP10600 BOM | 14 Jan 2015 | 123 | ||
| PMP10600 Schematic | 14 Jan 2015 | 325 |