High Voltage Half Bridge Design Guide for LMG3410 Smart GaN FET (Rev. A)

Texas Instruments

Published Date: 10 Nov 2018


As gallium nitride (GaN) power FETs become readily available for power designers to use, their promise of performance improvement with higher efficiencies and greater power densities can begin to become realized. By having better material properties over silicon, loss elements such as on-state resistance Rds(on) and output capacitance Coss are smaller for an equal die area. These GaN power FET devices, included in the LMG3410x family, are typically offered in high electron mobility transistor (HEMT) structures, which along with maximizing the material property benefits eliminate the reverse recovery Qrr when the device operates in third quadrant mode (conduction from source to drain). These benefits allow GaN power FETs to operate faster and at higher frequencies than previously capable. With typical slew rates around 30 V/ns to 100 V/ns at operating voltages around 380 V to 480 V, printed circuit board (PCB) layout optimization is even more essential since parasitic inductances and capacitances from poor layouts can drastically reduce performance or even prevent operation. When pushed to their limits to maximize system gains power GaN FETs provide the device can degrade and potentially overheat without a carefully designed thermal system to dissipate the generated heat. To prevent these problems from hampering designs and limiting performance layout recommendations, peripheral component selection and thermal system design are discussed.


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